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? semiconductor components industries, llc, 2017 august, 2017 ? rev. p0 1 publication order number: NCP81391/d NCP81391, NCP81391a advance information integrated driver and mosfet the NCP81391/a integrates a mosfet driver, high?side mosfet and low?side mosfet into a single package. the driver and mosfets have been opti mized for hig h?current dc?dc buck?boost power conversion applications. the NCP81391/a integrated solution greatly reduces package parasitics and board space compared to a discrete component solution. features ? capable of average currents up to 25 a ? capable of peak currents up to 65 a ? over 97% peak?efficiency ? compatible with 3.3 v and 5 v pwm inputs, with t ri?state ? zero current detection for improving light load efficiency ? optional thermal shutdown protection ? NCP81391: with thermal shutdown ? NCP81391a: no thermal shutdown ? internal bootstrap diode ? undervoltage lockout ? this is a pb?free device applications ? e?cigarettes ? unmanned aerial vehicles figure 1. application diagram (buck?boost) 5v ? 12v vccd vcc vin en pwm cgnd pgnd drvon from controller pwm1 from controller vin 4.5v ? 20v gh bst phase vsw gld glf vin vcc vccd gh bst cgnd pgnd en pwm phase gld glf vsw vout 5v ? 12v drvon from controller pwm2 from controller zcd_en# zcd_en1 from controller zcd_en# zcd_en2 from controller this document contains information on a new product. specifications and information herein are subject to change without notice. www.onsemi.com device package shipping ? ordering information NCP81391mntxg qfn31 (pb?free) 2500 / tape & reel (top view) pinout diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 81391 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 81391 alyw (note: microdot may be in either location) qfn31 5x5 case 485fg marking diagram NCP81391amntxg 5 4 3 2 1 6 7 8 20 21 22 23 19 18 17 13 9 10 16 15 14 28 27 31 30 29 24 25 26 phase pgnd2 cgnd en pwm zcd_en# vcc vccd nc9 vin16 vin15 vin14 vin13 nc12 gh bst vin17 pgnd23 pgnd22 pgnd21 pgnd20 vin19 vin18 vswh24 gld31 gld30 glf29 glf28 vswh25 vswh26 vswh27 11 12 32 pgnd flag 33 vin flag 34 glf
NCP81391, NCP81391a www. onsemi.com 2 figure 2. simplified block diagram dead time cntrl level shift uvlo glf vcc cgnd en pwm logic 45k vccd bst vin phase level shift 45k vswh pgnd temp sense shutdown clip gh zcd_en# vswh 3.84v for NCP81391/ no resistor for NCP81391a for NCP81391/ no tsd for NCP81391a 3.84v gld table 1. pin list and descriptions pin no. symbol description 1 phase bootstrap capacitor return 2 pgnd2 power ground 3 cgnd signal ground 4 en enable. there is a pull?down resistor to cgnd for the NCP81391. no pull?down resistor for NCP81391a. 5 pwm pwm control input: pwm = high hs fet is on, ls fet is off pwm = mid hs fet is off, ls fet is off pwm = low, zcd_en# = high hs fet is off, ls fet is on pwm = low, zcd_en# = low hs fet is off, ls fet is off when zero current is detected 6 zcd_en# zero current detect control. when this pin is at logic low, low?side fet will turn off when zero inductor current is detected (after a minimum blanking/de?bounce time). there is an internal pull?up resistor. 7 vcc control power supply input 8 vccd driver power supply input 9 nc9 no connect 10 bst bootstrap supply voltage. connect a mlcc capacitor of at least 0.1 f from this pin to phase. 11 gh high?side mosfet gate access. leave floating. 12 nc12 no connect 13 vin13 conversion supply power input 14 vin14 conversion supply power input 15 vin15 conversion supply power input
NCP81391, NCP81391a www. onsemi.com 3 table 1. pin list and descriptions pin no. description symbol 16 vin16 conversion supply power input 17 vin17 conversion supply power input 18 vin18 conversion supply power input 19 vin19 conversion supply power input 20 pgnd20 power ground 21 pgnd21 power ground 22 pgnd22 power ground 23 pgnd23 power ground 24 vswh24 switch node output 25 vswh25 switch node output 26 vswh26 switch node output 27 vswh27 switch node output 28 glf28 low?side mosfet gate access. pins 28, 29, 30 and 31 must be connected together on the pcb. 29 glf29 low?side mosfet gate access. pins 28, 29, 30 and 31 must be connected together on the pcb. 30 gld30 low?side driver gate access. pins 28, 29, 30 and 31 must be connected together on the pcb. 31 gld31 low?side driver gate access. pins 28, 29, 30 and 31 must be connected together on the pcb. 32 pgnd32 power ground flag 33 vin33 conversion supply power input flag 34 gl34 low side mosfet gate access. do not connect to pcb. see recommended pcb footprint for details. table 2. absolute maximum ratings (electrical information ? all signals referenced to pgnd unless noted otherwise) pin name v min v max unit vcc, vccd (dc) ?0.3 13.2 v vcc, vccd (< 100 ns) ? 15 v vin ?0.3 30 v bst (dc) ?0.3 35 v bst (< 1 0 ns) ?0.3 40 v bst to ph (dc) ?0.3 13.2 v vswh , phase (dc) ?0.3 30 v vswh , phase (< 10 ns) ?5 35 v gh (dc) ? v bst + 0.3 v gh wrt/ vswh (dc) ?0.3 13.2 v gh wrt/ vswh (< 200 ns) ?2 ? v gh wrt/ vswh (< 100 ns) ? 15 v gl (dc) ?0.3 v vcc + 0.3 v gl (< 200 ns) ?5 ? v gl (< 100 ns) ? 15 v en, zcd_en#, pwm ?0.3 6.5 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
NCP81391, NCP81391a www. onsemi.com 4 table 3. thermal information rating symbol value unit thermal resistance (note 1) j?a 23 c/w r j?bt 0.3 c/w r j?ct 0.5 c/w operating junction temperature range (note 2) t j ?40 to +150 c operating ambient temperature range t a ?40 to +125 c maximum storage temperature range t stg ?40 to +150 c maximum power dissipation p d 5.4 w moisture sensitivity level msl 3 1. jesd 51 - 7 (2s2p direct - attach method) with 0 lfm 2. the maximum package power dissipation must be observed . table 4. recommended operating conditions parameter pin name conditions min typ max unit supply voltage range vcc, vccd 4 . 5 12 13.2 v conversion voltage vin 4 . 5 12 20 v continuous output current f sw = 250 khz 25 a peak output current f sw = 250 khz, v vin = 12 v, v out = 6 v, duration = 10 ms, period = 1 s 65 a operating temperature ?40 100 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 5. electrical characteristics (v vcc = v vccd = 12 v, v vin = 12 v, v en = 5.0 v, c vccd = c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter symbol conditions min typ max unit vcc operating current i vcc_pwm en = 5 v, pwm = 250 khz ? ? 2 ma enabled, no switching i vcc_en en# = 5 v, pwm = 0 v, zcd_en# = 5 v ? ? 2 ma i vcc_zcd en# = 5 v, pwm = 0 v, zcd_en# = 0 v ? ? 2 ma disabled current i vcc_dis en = 0 v, zcd_en# = 5 v ? 960 1500 a i vcc_dis_zcd en = 0 v, zcd_en# = 0 v ? 960 1500 a uvlo threshold v uvlo vcc rising 3.8 4.35 4.5 v uvlo hysteresis v uvlo_hys 150 200 ? mv vccd supply current operating i vccd_pwm en = 5 v, pwm = 250 khz ? 47 70 ma enabled, no switching i vccd_en en = 5 v, pwm = 0 v NCP81391 ? ? 100 a en = 5 v, pwm = 0 v NCP81391a ? ? 100 a disabled i vccd_dis en = 0 v ? 60 100 a pwm input input high voltage v pwm_hi 2.6 ? ? v input mid voltage v pwm_mid 1.4 ? 1.8 v input low voltage v pwm_lo ? ? 0.6 v pwm input resistance r pwm ? 162 ? k pwm input bias voltage v pwm_bias pwm pin is floating ? 1.6 ? v
NCP81391, NCP81391a www. onsemi.com 5 table 5. electrical characteristics (v vcc = v vccd = 12 v, v vin = 12 v, v en = 5.0 v, c vccd = c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol pwm input input leakage i pwm_lk ? ? 5 a high side driver propagation delay, pwm falling t pwm,pd_f pwm = low to gh?vswh falling @ 90% ? 18 24 non?overlap delay , leading edge (note 3) t nol_l gl falling @ 1 v to gh?vswh rising @ 1 v 6 13 20 ns fall time, high?side gate t fdrvh gh falling, 90% to 10% ? 3.5 ? ns rise time, high?side gate t rdrvh gh rising, 10% to 90% ? 10 ? ns entering pwm mid - state propagation delay , high - to?mid t pwm_enter_h pwm = high?to?mid to gh?vswh falling @ 90% ? 20 ? ns exiting pwm mid - state propagation delay , mid - to?high t pwm_exit_h pwm = mid?to?high to gh?vswh rising @ 10% ? 13 25 ns low side driver propagation delay, pwm rising t pwm,pd_r pwm = high to gl falling @ 90% ? 15 22 ns non?overlap delay , trailing edge (note 3) t nol_t gh?vswh falling @ 1 v to gl rising @ 1 v 5 16 21 ns fall time, low?side gate t fdrvl gl falling, 90% to 10% ? 13 ? ns rise time, low?side gate t rdrvl gl rising, 10% to 90% ? 2.8 ? ns entering pwm mid - state propagation delay , low - to?mid t pwm_enter_l pwm = low?to?mid to gl falling @ 90% ? 30 ? ns exiting pwm mid - state propagation delay , mid - to?low t pwm_exit_l pwm = mid?to?low to gl rising @ 10% ? 13 25 ns mosfet n?channel high?side mosfet on resistance r on_hs from vin to vswh pin ? 2.0 ? m n?channel low?side mosfet on resistance r on_ls from vswh to pgnd pin ? 1.7 ? m en input input leakage i en_lk ncp8139 ? 20 ? a ncp8139a ? 50 ? na upper threshold v en_hi 2.0 ? ? v lower threshold v en_lo ? ? 0.8 v hysteresis v en_hys v en_hi ? v en_lo ? 470 ? mv en input resistance (NCP81391 only) r en pull?down resistance to cgnd ? 300 ? k enable delay time t en_on en rising @ v en_hi to gh?vswh rising @ 10%, pwm = high ? 30 ? ns disable delay time t en_off en falling @ v en_lo to gl falling @ 90%, pwm = low ? 15 40 ns zero current detection enable zcd_en# high v zcd_enb_hi 2.0 ? ? v zcd_en# low v zcd_enb_lo ? ? 0.8 v hysteresis v zcd_enb_hys ? 470 ? mv zcd_en# input resistance r zcd_enb pull?up resistance to internal 3.84 v ? 725 ? k zcd threshold v zcd_enb_th zcd_en# = 0 v, pwm = 0 v ? ?3 ? mv
NCP81391, NCP81391a www. onsemi.com 6 table 5. electrical characteristics (v vcc = v vccd = 12 v, v vin = 12 v, v en = 5.0 v, c vccd = c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?40 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol zero current detection enable zcd blanking + de?bounce timer t blank ? 130 ? ns thermal shutdown (for NCP81391 only) thermal shutdown temperature t thdn temperature at driver die ? 170 ? c thermal shutdown hysteresis t thdn_hys ? 20 ? c booststrap diode forward voltage v f_bst forward bias current = 2.0 ma 0.1 0.4 0.6 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. guaranteed by design and/or characterization. this parameter is not tested in production.
NCP81391, NCP81391a www. onsemi.com 7 typical characteristics figure 3. efficiency ? 12 v input, 500 khz figure 4. power loss ? 12 v input, 500 khz figure 5. efficiency ? 12 v input, 250 khz figure 6. power loss ? 12 v input, 250 khz figure 7. output current derating f sw = 250 khz; v in = 12 v; v cc = v ccd = 12 v; v out = 6 v; l = 720 nh
NCP81391, NCP81391a www. onsemi.com 8 applications information theory of operation low?side driver the low?side driver drives a ground?referenced low?r ds(on) n?channel mosfet. the voltage rail for the low?side driver is internally connected to vccd and cgnd. the gld pin connects directly to the output of the low?side driver. the glf pins connects directly to the gate of the low?side mosfet. see figure 2. gld and glf are not connected inside the package. for proper operation, these pins must be connected together on the pcb. high?side driver the high?side driver drives a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the phase pin, which is internally connected to the vswh pin. the bootstrap circuit is comprised of an internal diode and an external bootstrap capacitor. when the NCP81391/a is starting up, the vswh pin is at ground, so the bootstrap capacitor charges up to vccd through the bootstrap diode (see figure 1). when the pwm input goes high, the high?side driver will begin to turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the voltage at the vswh pin rises. when the high?side mosfet is fully on, the vswh voltage equals the vin voltage, with the bst voltage higher than vin by the amount of voltage on the bootstrap capacitor. the bootstrap capacitor is recharged when the switch node goes low during the next cycle. parasitic inductances and capacitances within the packaging and mosfets can cause significant ringing of the vswh signal during turn?on and turn?off of the high?side mosfet. when operating at high input voltages and high output currents, the peak ringing voltages on vswh could cause the drain?to?source voltage across the mosfets to exceed its maximum rating. including a resistor in series with the bootstrap capacitor can reduce the peak vswh ringing voltages. a resistor value of 4 is recommended when operating at vin voltages greater than 16 v. overlap protection circuit as pwm transitions between the logic high and logic low states, the driver circuitry prevents both mosfets from being on at the same time. while one mosfet is turned off, the driver monitors the gate voltage of that mosfet until it reaches 1 v. at this point, a non?overlap timer is started, and prevents the gate of the other mosfet from going high until this timer expires. in the electrical characteristics table, this non?overlap timer is specified as the time between 1 v of the falling gate and 10% of the high value of the rising gate. three?state pwm input switching pwm between logic?high and logic?low states allows the driver to operate in continuous conduction mode , as long as vcc is greater than the uvlo threshold and en is high. the pwm mid?state allows the NCP81391/a to enter a high?impedance mode, where both mosfets are off. table 6. en/pwm logic table en pwm zcd_en# gh gl low x x low low high low high low high high mid high low low high high high high low high low low low zcd high mid low low low high high low high low zero current detection at light load conditions, the inductor current can be negative due to the inductor current ripple. the zero current detection (zcd) function in the NCP81391/a can prevent negative current during these light load conditions. when zcd is active, the NCP81391/a will monitor the voltage at the vswh pins when the ls fet is on and conducting. there is a blanking/de?bounce timer that delays when this monitoring starts, from the time gl goes high. as the inductor current falls towards zero, the voltage on vswh will become less negative. when the vswh voltage reaches the zcd threshold, the ls fet is turned off. positive current can still flow through the body diode of the ls fet, but the body diode will block any current in the negative direction. zcd is activated by placing zcd_en# in the logic?low state. there is an internal pull?up resistor at the zcd_en# pin. whenever vcc rises above the uvlo threshold, an auto?calibration is conducted on the zcd threshold. during the auto?calibration, the driver outputs will remain low and not respond to the pwm input. the auto?calibration cycle takes 28 s to complete, typically. thermal shutdown with the NCP81391, if the driver temperature exceeds t thdn , the part will enter thermal shutdown and turn off both mosfets. after the temperature decreases to t thdn ? t thdn_hys , the part will resume normal operation. for applications that prefer not to have this power stage have a thermal shutdown, the NCP81391a removes the thermal shutdown protection feature. to distinguish between the NCP81391 and NCP81391a, externally, the NCP81391 has an internal pull?down resistor at the en pin while the NCP81391a does not have an internal pull?down resistor at the en pin.
NCP81391, NCP81391a www. onsemi.com 9 power supply decoupling the NCP81391/a sources relatively large currents into the mosfet gates. in order to maintain a constant and stable i nput supply voltage, low?esr capacitors should be placed between vcc and gnd and between vccd and ground, close to the NCP81391/a. a 1 f to 4.7 f multilayer ceramic capacitor (mlcc) is sufficient. to further filter noise from vccd from entering the vcc pin, placing a 10 resistor between the vcc and vccd pins is recommended. bootstrap circuit the bootstrap circuit uses an external charge storage capacitor (c bst ) and the internal bootstrap diode. the bootstrap capacitor should have a voltage rating twice the maximum vccd supply voltage. a bootstrap capacitance of at least 100 nf with a minimum 25 v rating is recommended. for best performances, use a 1 f ceramic capacitor. in order to prevent the bootstrap capacitor from discharging during conditions where the high side is turned on for a long time, such as high duty cycle or zcd, a maximum duty cycle must be respected. the maximum duty cycle depends on the two time constants that appear during the charging time (converter?s t off ) and discharging time (converter?s t on ). to keep the bootstrap capacitor charged, the following relation must kept. d rdrv (1 d) rbst 50 thus, dmax can be expressed as dmax 1 rbst rdrv 50 rbst with the converter?s duty cycle, r drv the high?side driver equivalent resistance from vbst to vswh (typically 5 k ) , r bst the bootstrap series resistor. note that the bootstrap capacitance has no effect on maximum duty cycle since it is common in both time constants. example: f sw = 250 khz, r drv = 5 k , r bst = 4 , the maximum duty cycle allowed to keep the bootstrap capacitor charged is d max = 96% and t on_max = d max /f sw = 3.84 s. pwm gl gh ? vswh t pwm,pd_r 90% tf drvl 10% 1v t nol_l 10% 90% tr drvh 1v 10% 90% 90% 10% t pwm,pd_f tf drvh t nol_t tr drvl 1v 1v figure 8. gate timing diagram
NCP81391, NCP81391a www. onsemi.com 10 pwm gh gl zcd_en# inductor current zcd_en# & pwm = low prevents negative current 0a 0v 0v 0v 0v gl pulls low when zero current is detected pwm = mid puts device into high?impedance state gl stays low with pwm in mid?state zcd_en# = high allows negative current figure 9. zero cross detect functionality figure 10. application schematic (buck?side)
NCP81391, NCP81391a www. onsemi.com 11 figure 11. recommended layout (buck?side)
NCP81391, NCP81391a www. onsemi.com 12 package dimensions qfn31 5x5, 0.5p case 485fg issue a
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